AMD plans to return to the dance of long-standing high-performance processors, for example with its Infinity Fabric to connect different chips in one box (a main processor and a graphics card, in particular). It seems that the manufacturer plans to push this technology a step further with "chiplets", that is to say very small chips that would be assembled in the same housing to form a complete processor. Each of these chips would be much smaller and cheaper to manufacture (we could make thousands on the same silicon wafer, rather than a few tens to hundreds of complete processors on the same surface). The housing interfacing all these chips could be much larger than today, incorporating more features: besides the computing cores, we could count the memory or the entirety of the power electronics. These small components would then communicate together using an interposer, a form of internal network to the housing. The idea is not exclusive to AMD: it is found at the base of some processors Xeon Scalable, where a refined version of the mechanism is used to include an FPGA, for example.
Nevertheless, this decomposition of the processors is not without problem. Indeed, with a very simple network, if the puclets are not well designed, the user runs the risk of having traffic jams, even a fatal hug: for example, if the puclets try to communicate in a circle, it is possible that all are waiting for the next ... and so nothing happens. The difficulty arises that, in a architecture based cups, it is impossible to predict all the paths that will be possible inside the housing, so all potentially dangerous situations for the entire system. If one begins to design all the pipettes simultaneously taking into account these possibilities, one breaks the advantage even of this approach: the pucets would be absolutely more independent and could not be more mixed arbitrarily.
AMD recently described its solution to avoid such disadvantages. Its engineers have found a fairly simple set of rules that ensure there is never a fatal hug, by restricting where data can enter and exit, and their direction. Thus, regardless of the composition of the pucets, it can be proved that the case will never experience a problem; one can conceive one of these pucets considering that the rest of the case is only one other pucet.
